%0 Conference Paper %1 conf/aspdac/IizukaIA04 %A Iizuka, Tetsuya %A Ikeda, Makoto %A Asada, Kunihiro %B ASP-DAC %D 2004 %E Imai, Masaharu %I IEEE Computer Society %K dblp %P 149-154 %T High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2004.html#IizukaIA04 %@ 0-7803-8175-0

@inproceedings{conf/aspdac/IizukaIA04, added-at = {2023-03-23T00:00:00.000+0100}, author = {Iizuka, Tetsuya and Ikeda, Makoto and Asada, Kunihiro}, biburl = {https://www.bibsonomy.org/bibtex/2fb714e8679b77a91e0c71e3b9a5647ac/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2004}, editor = {Imai, Masaharu}, ee = {https://dl.acm.org/citation.cfm?id=1015126}, interhash = {ef54f68e104b77241d793a836ab86f1a}, intrahash = {fb714e8679b77a91e0c71e3b9a5647ac}, isbn = {0-7803-8175-0}, keywords = {dblp}, pages = {149-154}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:15:59.000+0200}, title = {High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2004.html#IizukaIA04}, year = 2004 }