%0 Conference Paper %1 conf/vlsid/ChavdaJA98 %A Chavda, Pramit %A Jacob, James %A Agrawal, Vishwani D. %B VLSI Design %D 1998 %I IEEE Computer Society %K dblp %P 218-221 %T Optimizing Logic Design Using Boolean Transforms. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1998.html#ChavdaJA98 %@ 0-8186-8224-8

@inproceedings{conf/vlsid/ChavdaJA98, added-at = {2023-03-24T00:00:00.000+0100}, author = {Chavda, Pramit and Jacob, James and Agrawal, Vishwani D.}, biburl = {https://www.bibsonomy.org/bibtex/2e136feb8f1b1d3a1fa8ec184e7ae2fb2/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1998}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646605}, interhash = {3a6d2b49e329323fcea8c52aa815fe90}, intrahash = {e136feb8f1b1d3a1fa8ec184e7ae2fb2}, isbn = {0-8186-8224-8}, keywords = {dblp}, pages = {218-221}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:47:35.000+0200}, title = {Optimizing Logic Design Using Boolean Transforms.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1998.html#ChavdaJA98}, year = 1998 }