Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core.
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%0 Conference Paper
%1 conf/vlsic/ChoTKTKD16
%A Cho, Minki
%A Tokunaga, Carlos
%A Kim, Stephen T.
%A Tschanz, James W.
%A Khellah, Muhammad M.
%A De, Vivek
%B VLSI Circuits
%D 2016
%I IEEE
%K dblp
%P 1-2
%T Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core.
%U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#ChoTKTKD16
%@ 978-1-5090-0635-9
@inproceedings{conf/vlsic/ChoTKTKD16,
added-at = {2022-10-02T00:00:00.000+0200},
author = {Cho, Minki and Tokunaga, Carlos and Kim, Stephen T. and Tschanz, James W. and Khellah, Muhammad M. and De, Vivek},
biburl = {https://www.bibsonomy.org/bibtex/24800de1bc6e709f12ce38ad236113ce3/dblp},
booktitle = {VLSI Circuits},
crossref = {conf/vlsic/2016},
ee = {https://doi.org/10.1109/VLSIC.2016.7573529},
interhash = {47f6b2021dc2b834a22087906cc91128},
intrahash = {4800de1bc6e709f12ce38ad236113ce3},
isbn = {978-1-5090-0635-9},
keywords = {dblp},
pages = {1-2},
publisher = {IEEE},
timestamp = {2024-04-10T15:34:06.000+0200},
title = {Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core.},
url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#ChoTKTKD16},
year = 2016
}
