The Design is mainly Intended for High Speed Random Frequency Carrier Wave Generator of 1 Ebps Data Rate using 2e10-1 Tapped PRBS Pattern Sequence. The PRBS is Designed by using LFSR Linear Feed Back Shift Register & XOR Gate with Specific Tapping Points as per CCITT ITU Standards. RTL Design Architecture Implemented by using VHDL &/ Verilog HDL, Programming & Debugging Done by using Spartan III FPGA Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O
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%0 Journal Article
%1 N__2015
%A Sastry, Prof. P. N. V. M
%A Krishnaiah, Prof. G.
%A Rao, Prof. Dr. D. N.
%A Vathsal, Dr. S.
%D 2015
%I Auricle Technologies, Pvt., Ltd.
%J International Journal on Recent and Innovation Trends in Computing and Communication
%K & CCITT Circuit Committee Consulting Description Feedback Hardware High ITU Integrated International LFSR-Linear Language Level PRBS-Pseudo R RTL- Register Shift Speed Telecom Telegraph Transfer Unit VHDL- Very for –
%N 1
%P 264--267
%R 10.17762/ijritcc2321-8169.150153
%T HDL Design for Exa Hertz Clock Based 2e10-1 Exa Bits Per Second (Ebps) PRBS IP Core Generator for Ultra High Speed Wireless Communication Products
%U http://dx.doi.org/10.17762/ijritcc2321-8169.150153
%V 3
%X The Design is mainly Intended for High Speed Random Frequency Carrier Wave Generator of 1 Ebps Data Rate using 2e10-1 Tapped PRBS Pattern Sequence. The PRBS is Designed by using LFSR Linear Feed Back Shift Register & XOR Gate with Specific Tapping Points as per CCITT ITU Standards. RTL Design Architecture Implemented by using VHDL &/ Verilog HDL, Programming & Debugging Done by using Spartan III FPGA Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O
@article{N__2015,
abstract = {The Design is mainly Intended for High Speed Random Frequency Carrier Wave Generator of 1 Ebps Data Rate using 2e10-1 Tapped PRBS Pattern Sequence. The PRBS is Designed by using LFSR Linear Feed Back Shift Register & XOR Gate with Specific Tapping Points as per CCITT ITU Standards. RTL Design Architecture Implemented by using VHDL &/ Verilog HDL, Programming & Debugging Done by using Spartan III FPGA Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O},
added-at = {2015-08-03T09:09:50.000+0200},
author = {Sastry, Prof. P. N. V. M and Krishnaiah, Prof. G. and Rao, Prof. Dr. D. N. and Vathsal, Dr. S.},
biburl = {https://www.bibsonomy.org/bibtex/23ead92c496dbd4acec9577fa37c445e6/ijritcc},
doi = {10.17762/ijritcc2321-8169.150153},
interhash = {4dfaa99451e480674746493bc8eb42af},
intrahash = {3ead92c496dbd4acec9577fa37c445e6},
journal = {International Journal on Recent and Innovation Trends in Computing and Communication},
keywords = {& CCITT Circuit Committee Consulting Description Feedback Hardware High ITU Integrated International LFSR-Linear Language Level PRBS-Pseudo R RTL- Register Shift Speed Telecom Telegraph Transfer Unit VHDL- Very for –},
month = {january},
number = 1,
pages = {264--267},
publisher = {Auricle Technologies, Pvt., Ltd.},
timestamp = {2015-08-03T09:09:50.000+0200},
title = {{HDL} Design for Exa Hertz Clock Based 2e10-1 Exa Bits Per Second (Ebps) {PRBS} {IP} Core Generator for Ultra High Speed Wireless Communication Products},
url = {http://dx.doi.org/10.17762/ijritcc2321-8169.150153},
volume = 3,
year = 2015
}