%0 Conference Paper %1 10.1007/978-3-031-42921-7_21 %A Knödtel, Johannes %A Muñoz Hernandez, Hector Gerardo %A Lehnert, Alexander %A Thieu, Gia Bao %A Gesper, Sven %A Payá-Vayá, Guillermo %A Reichenbach, Marc %B Applied Reconfigurable Computing. Architectures, Tools, and Applications %C Cham %D 2023 %E Palumbo, Francesca %E Keramidas, Georgios %E Voros, Nikolaos %E Diniz, Pedro C. %I Springer Nature Switzerland %K myown %P 307--321 %T TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs %X The use of High Bandwidth Memory (HBM) is one way to solve the bottleneck of memory bandwidth limitation. Furthermore, the integration of HBM memories in Field Programmable Gate Arrays (FPGA) now also makes it possible to use this memory technology in a wide range of applications and even in embedded systems. Nevertheless, the use of HBM poses major challenges for architecture development. In addition to highly parallel access, high latencies must be hidden. Furthermore, the partitioning of the data and the bus structure play a decisive role. Finally, memory controller implementations are mostly vendor specific making it difficult to predict the exact performance of the memory subsystem. In this paper, we present TAPRE-HBM, an FPGA-based rapid prototyping platform for analyzing computer architectures with HBM memory backends. The goal of this work is to evaluate and assess the impact of particular memory access patterns. As these patterns are an emerging property of the architecture and application, such traces can be created by simulating the target computer architectures which should use the HBM memory subsystem without the need for a specific implementation or integration. Any incurred latency will be revealed by this method, even if only a system-level model exists. Using the FPGA-based rapid prototyping platform, performance predictions can be made and thus it can be determined whether the selected target architecture or software running on the target architecture is suitable for use with HBM memories. The proposed platform is analyzed using a vector processor as an example and present various optimizations to increase the memory bandwidth. Compared to other works, a high number of memory transactions can be simulated on real hardware, with a high memory interface frequency and arbitrary delays between transactions. %@ 978-3-031-42921-7

@inproceedings{10.1007/978-3-031-42921-7_21, abstract = {The use of High Bandwidth Memory (HBM) is one way to solve the bottleneck of memory bandwidth limitation. Furthermore, the integration of HBM memories in Field Programmable Gate Arrays (FPGA) now also makes it possible to use this memory technology in a wide range of applications and even in embedded systems. Nevertheless, the use of HBM poses major challenges for architecture development. In addition to highly parallel access, high latencies must be hidden. Furthermore, the partitioning of the data and the bus structure play a decisive role. Finally, memory controller implementations are mostly vendor specific making it difficult to predict the exact performance of the memory subsystem. In this paper, we present TAPRE-HBM, an FPGA-based rapid prototyping platform for analyzing computer architectures with HBM memory backends. The goal of this work is to evaluate and assess the impact of particular memory access patterns. As these patterns are an emerging property of the architecture and application, such traces can be created by simulating the target computer architectures which should use the HBM memory subsystem without the need for a specific implementation or integration. Any incurred latency will be revealed by this method, even if only a system-level model exists. Using the FPGA-based rapid prototyping platform, performance predictions can be made and thus it can be determined whether the selected target architecture or software running on the target architecture is suitable for use with HBM memories. The proposed platform is analyzed using a vector processor as an example and present various optimizations to increase the memory bandwidth. Compared to other works, a high number of memory transactions can be simulated on real hardware, with a high memory interface frequency and arbitrary delays between transactions.}, added-at = {2024-02-05T15:15:37.000+0100}, address = {Cham}, author = {Knödtel, Johannes and Muñoz Hernandez, Hector Gerardo and Lehnert, Alexander and Thieu, Gia Bao and Gesper, Sven and Payá-Vayá, Guillermo and Reichenbach, Marc}, biburl = {https://www.bibsonomy.org/bibtex/2ed6abf2263c8e828ae11bbe884a10194/eisl3s}, booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications}, description = {TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs | SpringerLink}, editor = {Palumbo, Francesca and Keramidas, Georgios and Voros, Nikolaos and Diniz, Pedro C.}, interhash = {523ec9e92c744c162456260c321cf78d}, intrahash = {ed6abf2263c8e828ae11bbe884a10194}, isbn = {978-3-031-42921-7}, keywords = {myown}, pages = {307--321}, publisher = {Springer Nature Switzerland}, timestamp = {2024-02-05T15:15:37.000+0100}, title = {TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs}, year = 2023 }