%0 Journal Article %1 journals/tvlsi/ChenLKSLXR10 %A Chen, Yiran %A Li, Hai %A Koh, Cheng-Kok %A Sun, Guangyu %A Li, Jing %A Xie, Yuan %A Roy, Kaushik %D 2010 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 11 %P 1621-1624 %T Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi18.html#ChenLKSLXR10 %V 18

@article{journals/tvlsi/ChenLKSLXR10, added-at = {2022-07-04T00:00:00.000+0200}, author = {Chen, Yiran and Li, Hai and Koh, Cheng-Kok and Sun, Guangyu and Li, Jing and Xie, Yuan and Roy, Kaushik}, biburl = {https://www.bibsonomy.org/bibtex/2990412e7b47422b237107aac94dc4c0d/dblp}, ee = {https://doi.org/10.1109/TVLSI.2009.2026280}, interhash = {5fe4ab25a1a4083fba74eef32deef9bf}, intrahash = {990412e7b47422b237107aac94dc4c0d}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 11, pages = {1621-1624}, timestamp = {2024-04-08T14:32:25.000+0200}, title = {Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi18.html#ChenLKSLXR10}, volume = 18, year = 2010 }