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Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.

Y. Chen, H. Li, C. Koh, G. Sun, J. Li, Y. Xie, and K. Roy. IEEE Trans. Very Large Scale Integr. Syst., 18 (11): 1621-1624 (2010)

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Guangyu Wang

Guangyu Zhou

Guangyu Fu

Guangyu Wang

Guangyu Zhu

Other publications of authors with the same name

An efficient compiler framework for cache bypassing on GPUs.X. Xie, Y. Liang, G. Sun, and D. Chen. ICCAD, page 516-523. IEEE, (2013)Optimal reference subset selection for nearest neighbor classification by tabu search.H. Zhang, and G. Sun. Pattern Recognit., 35 (7): 1481-1490 (2002)GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.G. Dai, T. Huang, Y. Chi, J. Zhao, G. Sun, Y. Liu, Y. Wang, Y. Xie, and H. Yang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 640-653 (2019)Performance-centric register file design for GPUs using racetrack memory.S. Wang, Y. Liang, C. Zhang, X. Xie, G. Sun, Y. Liu, Y. Wang, and X. Li. ASP-DAC, page 25-30. IEEE, (2016)Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power.C. Zhang, G. Sun, W. Zhang, F. Mi, H. Li, and W. Zhao. ASP-DAC, page 100-105. IEEE, (2015)Fabrication cost analysis for 2D, 2.5D, and 3D IC designs.C. Zhang, and G. Sun. 3DIC, page 1-4. IEEE, (2011)COPPER: a combinatorial optimization problem solver with processing-in-memory architecture.Q. Wang, X. Li, B. Wu, K. Yang, W. Hu, G. Sun, and Y. Yang. Frontiers Inf. Technol. Electron. Eng., 24 (5): 731-741 (May 2023)A Nonlinear Three-Phase Phase-Locked Loop Based on Linear Active Disturbance Rejection Controller.G. Sun, Y. Li, W. Jin, and L. Bu. IEEE Access, (2017)Three-dimensional Integrated Circuits: Design, EDA, and Architecture.G. Sun, Y. Chen, X. Dong, J. Ouyang, and Y. Xie. Foundations and Trends in Electronic Design Automation, 5 (1-2): 1-151 (2011)Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory.G. Sun, E. Kursun, J. Rivers, and Y. Xie. JETC, 9 (3): 22:1-22:22 (2013)

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Disambiguation of "Sun, Guangyu"

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Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.

Please choose a person to relate this publication to

Guangyu Wang

Guangyu Zhou

Guangyu Fu

Guangyu Wang

Guangyu Zhu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sun, Guangyu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.

Please choose a person to relate this publication to

Guangyu Wang

Guangyu Zhou

Guangyu Fu

Guangyu Wang

Guangyu Zhu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.