%0 Journal Article %1 journals/tcad/SamalSKDL17 %A Samal, Sandeep Kumar %A Samadi, Kambiz %A Kamal, Pratyush %A Du, Yang %A Lim, Sung Kyu %D 2017 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 6 %P 992-1003 %T Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs. %U http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#SamalSKDL17 %V 36

@article{journals/tcad/SamalSKDL17, added-at = {2022-10-02T00:00:00.000+0200}, author = {Samal, Sandeep Kumar and Samadi, Kambiz and Kamal, Pratyush and Du, Yang and Lim, Sung Kyu}, biburl = {https://www.bibsonomy.org/bibtex/231618982b3c97b4b94064a2d85914dd9/dblp}, ee = {https://doi.org/10.1109/TCAD.2016.2616377}, interhash = {668d7cb7279ab0cc7163386c74f71966}, intrahash = {31618982b3c97b4b94064a2d85914dd9}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 6, pages = {992-1003}, timestamp = {2024-04-08T19:45:55.000+0200}, title = {Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#SamalSKDL17}, volume = 36, year = 2017 }