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Disambiguation of "Samadi, Kambiz"

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Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (6): 992-1003 (2017)

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Samadi

Behzad Samadi

Fatemeh Samadi

Aliresa Samadi

Kambiz Norozi

 

Other publications of authors with the same name

Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (6): 992-1003 (2017)Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology., , , , and . DATE, page 842-847. IEEE, (2019)ORION 2.0: A Power-Area Simulator for Interconnection Networks., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 191-196 (2012)Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs., , , and . ISPD, page 47-54. ACM, (2014)Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations., , , and . ICCAD, page 256-263. IEEE, (2010)Quantified Impacts of Guardband Reduction on Design Process Outcomes., , and . ISQED, page 790-797. IEEE Computer Society, (2008)Improved on-chip router analytical power and area modeling., , and . ASP-DAC, page 241-246. IEEE, (2010)BEOL stack-aware routability prediction from placement using data mining techniques., , , , and . ICCD, page 41-48. IEEE Computer Society, (2016)GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks., , , and . ISCA, page 650-661. IEEE Computer Society, (2018)SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks., , , , and . ISCA, page 662-673. IEEE Computer Society, (2018)