%0 Conference Paper %1 conf/aicas/WuHC22 %A Wu, Chung-Bin %A Hsiao, Yu-Kuan %A Chang, Wei-Hsuan %B AICAS %D 2022 %I IEEE %K dblp %P 238-241 %T Extensible and Modularized Processing Unit Design and Implementation for AI Accelerator. %U http://dblp.uni-trier.de/db/conf/aicas/aicas2022.html#WuHC22 %@ 978-1-6654-0996-4

@inproceedings{conf/aicas/WuHC22, added-at = {2022-09-16T00:00:00.000+0200}, author = {Wu, Chung-Bin and Hsiao, Yu-Kuan and Chang, Wei-Hsuan}, biburl = {https://www.bibsonomy.org/bibtex/23d670e4751083f8beaba0d270e552a9d/dblp}, booktitle = {AICAS}, crossref = {conf/aicas/2022}, ee = {https://doi.org/10.1109/AICAS54282.2022.9869949}, interhash = {6ee97fb152fa72f073d4a0fe1650db31}, intrahash = {3d670e4751083f8beaba0d270e552a9d}, isbn = {978-1-6654-0996-4}, keywords = {dblp}, pages = {238-241}, publisher = {IEEE}, timestamp = {2024-04-09T17:51:00.000+0200}, title = {Extensible and Modularized Processing Unit Design and Implementation for AI Accelerator.}, url = {http://dblp.uni-trier.de/db/conf/aicas/aicas2022.html#WuHC22}, year = 2022 }