%0 Journal Article %1 journals/jssc/GerosaAACDKNNPR97 %A Gerosa, Gianfranco %A Alexander, Mike %A Alvarez, Jose %A Croxton, Cody %A D'Addeo, Michael %A Kennedy, A. Richard %A Nicoletta, Carmine %A Nissen, James P. %A Philip, Ross %A Reed, Paul %A Sanchez, Hector %A Taylor, Scott A. %A Burgess, Brad %D 1997 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 1635-1649 %T A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller. %U http://dblp.uni-trier.de/db/journals/jssc/jssc32.html#GerosaAACDKNNPR97 %V 32

@article{journals/jssc/GerosaAACDKNNPR97, added-at = {2022-07-07T00:00:00.000+0200}, author = {Gerosa, Gianfranco and Alexander, Mike and Alvarez, Jose and Croxton, Cody and D'Addeo, Michael and Kennedy, A. Richard and Nicoletta, Carmine and Nissen, James P. and Philip, Ross and Reed, Paul and Sanchez, Hector and Taylor, Scott A. and Burgess, Brad}, biburl = {https://www.bibsonomy.org/bibtex/28287959c11dd557765e9ed43fa4b5c34/dblp}, ee = {https://doi.org/10.1109/4.641684}, interhash = {85692bc600d55561fce55d4831db0129}, intrahash = {8287959c11dd557765e9ed43fa4b5c34}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {1635-1649}, timestamp = {2024-04-08T10:44:44.000+0200}, title = {A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc32.html#GerosaAACDKNNPR97}, volume = 32, year = 1997 }