%0 Conference Paper %1 conf/fpl/TeradaUISTU12 %A Terada, Kazuhiko %A Uzawa, Hiroyuki %A Ikeda, Namiko %A Shigematsu, Satoshi %A Tanaka, Nobuyuki %A Urano, Masami %B FPL %D 2012 %E Koch, Dirk %E Singh, Satnam %E Tørresen, Jim %I IEEE %K dblp %P 639-642 %T Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2012.html#TeradaUISTU12 %@ 978-1-4673-2257-7

@inproceedings{conf/fpl/TeradaUISTU12, added-at = {2017-05-21T00:00:00.000+0200}, author = {Terada, Kazuhiko and Uzawa, Hiroyuki and Ikeda, Namiko and Shigematsu, Satoshi and Tanaka, Nobuyuki and Urano, Masami}, biburl = {https://www.bibsonomy.org/bibtex/2a255642331164837dcba7ab093dd48d4/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2012}, editor = {Koch, Dirk and Singh, Satnam and Tørresen, Jim}, ee = {https://doi.org/10.1109/FPL.2012.6339229}, interhash = {a095fca0d13a5c4ffca14203ce467d6e}, intrahash = {a255642331164837dcba7ab093dd48d4}, isbn = {978-1-4673-2257-7}, keywords = {dblp}, pages = {639-642}, publisher = {IEEE}, timestamp = {2019-10-17T19:14:05.000+0200}, title = {Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2012.html#TeradaUISTU12}, year = 2012 }