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s-class large-scale NW SoC using multiple FPGAs.

K. Terada, H. Uzawa, N. Ikeda, S. Shigematsu, N. Tanaka, and M. Urano. FPL, page 639-642. IEEE, (2012)

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Satoshi Ejima

Satoshi Okawa

Satoshi Otomo

Satoshi Murayama

Satoshi Nishida

Other publications of authors with the same name

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits.S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada. IEEE J. Solid State Circuits, 32 (6): 861-869 (1997)A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application.S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, T. Kaneko, and J. Yamada. IEEE J. Solid State Circuits, 31 (11): 1795-1802 (1996)A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs.H. Morimura, S. Shigematsu, T. Shimamura, K. Machida, and H. Kyuragi. IEEE J. Solid State Circuits, 37 (10): 1300-1306 (2002)A novel DBA scheme for TDM-PON based mobile fronthaul.T. Tashiro, S. Kuwano, J. Terada, T. Kawamura, N. Tanaka, S. Shigematsu, and N. Yoshimoto. OFC, page 1-3. IEEE, (2014)5G R&D Activities for High Capacity Technologies with Ultra High-Density Multi-Band and Multi-Access Layered Cells.M. Minowa, H. Seki, Y. Okumura, S. Suyama, J. Terada, S. Shigematsu, Y. Takatori, H. Asano, Y. Hirano, Y. Yamao and 2 other author(s). VTC Spring, page 1-5. IEEE, (2019)Fingerprint Image Enhancement by Pixel-Parallel Processing.N. Ikeda, M. Nakanishi, K. Fujii, T. Hatano, S. Shigematsu, T. Adachi, Y. Okazaki, and H. Kyuragi. ICPR (3), page 752-755. IEEE Computer Society, (2002)Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI.S. Shigematsu, H. Morimura, T. Shimamura, T. Hatano, N. Ikeda, Y. Okazaki, K. Machida, and M. Nakanishi. IEICE Trans. Electron., 90-C (10): 1892-1899 (2007)A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table.Y. Kawamura, K. Imamura, N. Miura, M. Urano, S. Shigematsu, and Y. Matsuda. ISPACS, page 351-356. IEEE, (2015)1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS.S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada. IEEE J. Solid State Circuits, 30 (8): 847-854 (August 1995)Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.K. Terada, H. Uzawa, N. Ikeda, S. Shigematsu, N. Tanaka, and M. Urano. FPL, page 639-642. IEEE, (2012)

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Disambiguation of "Shigematsu, Satoshi"

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Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.

Please choose a person to relate this publication to

Satoshi Ejima

Satoshi Okawa

Satoshi Otomo

Satoshi Murayama

Satoshi Nishida

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Shigematsu, Satoshi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.

Please choose a person to relate this publication to

Satoshi Ejima

Satoshi Okawa

Satoshi Otomo

Satoshi Murayama

Satoshi Nishida

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.