%0 Conference Paper %1 conf/vlsi/FesquetDJLRDBME19 %A Fesquet, Laurent %A Decoudu, Yoan %A Jadue, Alexis Rodrigo Iga %A de Paiva Leite, Thiago Ferreira %A Rolloff, Otto Aureliano %A Diallo, M. %A Bastos, Rodrigo Possamai %A Morin-Allory, Katell %A Engels, Sylvain %B VLSI-SoC %D 2019 %I IEEE %K dblp %P 27-32 %T A Distributed Body-Biasing Strategy for Asynchronous Circuits. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2019.html#FesquetDJLRDBME19 %@ 978-1-7281-3915-9

@inproceedings{conf/vlsi/FesquetDJLRDBME19, added-at = {2019-12-13T00:00:00.000+0100}, author = {Fesquet, Laurent and Decoudu, Yoan and Jadue, Alexis Rodrigo Iga and de Paiva Leite, Thiago Ferreira and Rolloff, Otto Aureliano and Diallo, M. and Bastos, Rodrigo Possamai and Morin-Allory, Katell and Engels, Sylvain}, biburl = {https://www.bibsonomy.org/bibtex/26a294678cf282010d358dd4f876163e5/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2019}, ee = {https://doi.org/10.1109/VLSI-SoC.2019.8920340}, interhash = {ac4b115fd49086c5b59871a9a7d5fb7a}, intrahash = {6a294678cf282010d358dd4f876163e5}, isbn = {978-1-7281-3915-9}, keywords = {dblp}, pages = {27-32}, publisher = {IEEE}, timestamp = {2019-12-14T11:40:42.000+0100}, title = {A Distributed Body-Biasing Strategy for Asynchronous Circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2019.html#FesquetDJLRDBME19}, year = 2019 }