( en | de | ru )

 

Disambiguation of "Morin-Allory, Katell"

Author of the publication

copydeleteadd this publication to your clipboard
A Distributed Body-Biasing Strategy for Asynchronous Circuits.

, , , , , , , , and . VLSI-SoC, page 27-32. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Katell Morin-Allory

Gabriel Morin

Helga Morin

Dieter Morin

Luce Morin

 

Other publications of authors with the same name

From High-Level Synthesis to Bundled-Data Circuits., , , and . SAMOS, volume 12471 of Lecture Notes in Computer Science, page 200-212. Springer, (2020)A High-Level Design Flow for Locally Body Biased Asynchronous Circuits., , and . VLSI-SoC, page 1-6. IEEE, (2021)Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems., , , , , , , , and . DDECS, page 1-4. IEEE, (2020)FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method., , and . ISVLSI, page 170-175. IEEE, (2021)Mining Missing Assumptions from Counter-Examples., , and . ACM Trans. Embed. Comput. Syst., 18 (1): 3:1-3:25 (2019)Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism., , , , , , , , and . VLSI-SoC, page 1-6. IEEE, (2021)A Generic CDC Modeling for Data Stability Verification., , , and . ICECS, page 1-4. IEEE, (2023)A Distributed Body-Biasing Strategy for Asynchronous Circuits., , , , , , , , and . VLSI-SoC, page 27-32. IEEE, (2019)Method for Data-Driven Pruning in Micropipeline Circuits., , , , , and . VLSI-SoC, page 1-6. IEEE, (2023)Formal Temporal Characterization of Register Vulnerability in Digital Circuits., , , and . ISVLSI, page 1-6. IEEE, (2023)