%0 Journal Article %1 journals/cssp/DwivediGL17 %A Dwivedi, Atul Kumar %A Ghosh, Subhojit %A Londhe, Narendra D. %D 2017 %J Circuits Syst. Signal Process. %K dblp %N 1 %P 156-180 %T Low-Power FIR Filter Design Using Hybrid Artificial Bee Colony Algorithm with Experimental Validation Over FPGA. %U http://dblp.uni-trier.de/db/journals/cssp/cssp36.html#DwivediGL17 %V 36

@article{journals/cssp/DwivediGL17, added-at = {2023-03-21T00:00:00.000+0100}, author = {Dwivedi, Atul Kumar and Ghosh, Subhojit and Londhe, Narendra D.}, biburl = {https://www.bibsonomy.org/bibtex/287313b7a2911559e6fad97fe4d514df6/dblp}, ee = {https://doi.org/10.1007/s00034-016-0297-4}, interhash = {bb399f6b520f64394ac1be16ba519f28}, intrahash = {87313b7a2911559e6fad97fe4d514df6}, journal = {Circuits Syst. Signal Process.}, keywords = {dblp}, number = 1, pages = {156-180}, timestamp = {2024-04-08T15:53:38.000+0200}, title = {Low-Power FIR Filter Design Using Hybrid Artificial Bee Colony Algorithm with Experimental Validation Over FPGA.}, url = {http://dblp.uni-trier.de/db/journals/cssp/cssp36.html#DwivediGL17}, volume = 36, year = 2017 }