%0 Journal Article %1 journals/ibmrd/ChesebroACEFHMNSVW95 %A Chesebro, Donald G. %A Adkisson, James W. %A Clark, Lyman R. %A Eslinger, Steven N. %A Faucher, Margaret A. %A Holmes, Steven J. %A Mallette, Raymond P. %A Nowak, Edward J. %A Sengle, Edward W. %A Voldman, Steven H. %A Weeks, Thomas W. %D 1995 %J IBM J. Res. Dev. %K dblp %N 1-2 %P 189-200 %T Overview of gate linewidth control in the manufacture of CMOS logic chips. %U http://dblp.uni-trier.de/db/journals/ibmrd/ibmrd39.html#ChesebroACEFHMNSVW95 %V 39

@article{journals/ibmrd/ChesebroACEFHMNSVW95, added-at = {2020-03-13T00:00:00.000+0100}, author = {Chesebro, Donald G. and Adkisson, James W. and Clark, Lyman R. and Eslinger, Steven N. and Faucher, Margaret A. and Holmes, Steven J. and Mallette, Raymond P. and Nowak, Edward J. and Sengle, Edward W. and Voldman, Steven H. and Weeks, Thomas W.}, biburl = {https://www.bibsonomy.org/bibtex/26ad11266696b48322c7358d4575b2f32/dblp}, ee = {https://doi.org/10.1147/rd.391.0189}, interhash = {c1180e355c68eee552f9f0064f4e4cf8}, intrahash = {6ad11266696b48322c7358d4575b2f32}, journal = {IBM J. Res. Dev.}, keywords = {dblp}, number = {1-2}, pages = {189-200}, timestamp = {2020-03-14T11:49:25.000+0100}, title = {Overview of gate linewidth control in the manufacture of CMOS logic chips.}, url = {http://dblp.uni-trier.de/db/journals/ibmrd/ibmrd39.html#ChesebroACEFHMNSVW95}, volume = 39, year = 1995 }