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Overview of gate linewidth control in the manufacture of CMOS logic chips.

D. Chesebro, J. Adkisson, L. Clark, S. Eslinger, M. Faucher, S. Holmes, R. Mallette, E. Nowak, E. Sengle, S. Voldman, and T. Weeks. IBM J. Res. Dev., 39 (1-2): 189-200 (1995)

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Edward J Birkenbeil

Edward J Laarman

Edward Fischer

Edward Sobel

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Critical reliability challenges in scaling SiO2-based dielectric to its limit.E. Wu, J. Suñé, W. Lai, A. Vayshenker, E. Nowak, and D. Harmon. Microelectron. Reliab., 43 (8): 1175-1184 (2003)A Retrospective View on the Technology Evolution to Support Low Power Mobile Application.B. Paul, A. Jacob, W. Taylor, R. Mann, J. Versaggi, E. Nowak, and L. Liebmann. J. Low Power Electron., 14 (3): 374-392 (2018)Practical performance/power alternatives within an existing CMOS technology generation.K. Bernstein, J. Bertsch, W. Clark, J. Ellis-Monaghan, L. Heller, and E. Nowak. ISLPED, page 365-370. IEEE, (1996)Effective Drive Current in Scaled FinFET and NSFET CMOS Inverters.A. Razavieh, Y. Deng, P. Zeitzoff, M. Na, J. Frougier, G. Karve, D. Brown, T. Yamashita, and E. Nowak. DRC, page 1-2. IEEE, (2018)High Performance Double-Gate Device Technology Challenges and Opportunities (invited).M. Leong, H. Wong, E. Nowak, J. Kedzierski, and E. Jones. ISQED, page 492-495. IEEE Computer Society, (2002)Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges.J. Goo, R. Williams, G. Workman, Q. Chen, S. Lee, and E. Nowak. CICC, page 265-272. IEEE, (2008)Overview of gate linewidth control in the manufacture of CMOS logic chips.D. Chesebro, J. Adkisson, L. Clark, S. Eslinger, M. Faucher, S. Holmes, R. Mallette, E. Nowak, E. Sengle, S. Voldman and 1 other author(s). IBM J. Res. Dev., 39 (1-2): 189-200 (1995)CMOS scaling into the 21st century: 0.1 µm and beyond.Y. Taur, Y. Mii, D. Frank, H. Wong, D. Buchanan, S. Wind, S. Rishton, W. Sai-Halasz, and E. Nowak. IBM J. Res. Dev., 39 (1-2): 245-260 (1995)Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor.K. Bernstein, J. Bertsch, L. Heller, E. Nowak, and F. White. IBM J. Res. Dev., 39 (1-2): 33-42 (1995)Silicon CMOS devices beyond scaling.W. Haensch, E. Nowak, R. Dennard, P. Solomon, A. Bryant, O. Dokumaci, A. Kumar, X. Wang, J. Johnson, and M. Fischetti. IBM J. Res. Dev., 50 (4-5): 339-362 (2006)

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Disambiguation of "Nowak, Edward J."

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Overview of gate linewidth control in the manufacture of CMOS logic chips.

Please choose a person to relate this publication to

Edward J Birkenbeil

Edward J Birkenbeil

Edward J Laarman

Edward Fischer

Edward Sobel

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Nowak, Edward J."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Overview of gate linewidth control in the manufacture of CMOS logic chips.

Please choose a person to relate this publication to

Edward J Birkenbeil

Edward J Birkenbeil

Edward J Laarman

Edward Fischer

Edward Sobel

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Overview of gate linewidth control in the manufacture of CMOS logic chips.