%0 Journal Article %1 journals/jssc/YehW15 %A Yeh, Chih-Wei Stanley %A Wong, S. Simon %D 2015 %J IEEE J. Solid State Circuits %K dblp %N 5 %P 1299-1309 %T Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology. %U http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#YehW15 %V 50

@article{journals/jssc/YehW15, added-at = {2020-08-30T00:00:00.000+0200}, author = {Yeh, Chih-Wei Stanley and Wong, S. Simon}, biburl = {https://www.bibsonomy.org/bibtex/2ff197365b265d2ca93059d18b2025451/dblp}, ee = {https://doi.org/10.1109/JSSC.2015.2402217}, interhash = {c8f5849fda7cfa771de631e846db9410}, intrahash = {ff197365b265d2ca93059d18b2025451}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 5, pages = {1299-1309}, timestamp = {2020-08-31T11:40:57.000+0200}, title = {Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#YehW15}, volume = 50, year = 2015 }