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%0 Conference Paper
%1 conf/cisis/GuoLPHCDW08
%A Guo, Jianjun
%A che Lai, Ming
%A Pang, Zhengyuan
%A Huang, Libo
%A Chen, Fangyuan
%A Dai, Kui
%A Wang, Zhiying
%B CISIS
%D 2008
%E Xhafa, Fatos
%E Barolli, Leonard
%I IEEE Computer Society
%K dblp
%P 601-606
%T Memory System Design for a Multi-core Processor.
%U http://dblp.uni-trier.de/db/conf/cisis/cisis2008.html#GuoLPHCDW08
%@ 978-0-7695-3109-0
@inproceedings{conf/cisis/GuoLPHCDW08,
added-at = {2023-03-24T00:00:00.000+0100},
author = {Guo, Jianjun and che Lai, Ming and Pang, Zhengyuan and Huang, Libo and Chen, Fangyuan and Dai, Kui and Wang, Zhiying},
biburl = {https://www.bibsonomy.org/bibtex/2c141c177f80332a16b8fc70f609e914d/dblp},
booktitle = {CISIS},
crossref = {conf/cisis/2008},
editor = {Xhafa, Fatos and Barolli, Leonard},
ee = {https://doi.ieeecomputersociety.org/10.1109/CISIS.2008.39},
interhash = {d1fa0ddd629a484477cb8d40b446ecfd},
intrahash = {c141c177f80332a16b8fc70f609e914d},
isbn = {978-0-7695-3109-0},
keywords = {dblp},
pages = {601-606},
publisher = {IEEE Computer Society},
timestamp = {2024-04-10T04:53:05.000+0200},
title = {Memory System Design for a Multi-core Processor.},
url = {http://dblp.uni-trier.de/db/conf/cisis/cisis2008.html#GuoLPHCDW08},
year = 2008
}