%0 Conference Paper %1 conf/dac/KulkarniDV17 %A Kulkarni, Niranjan %A Dengi, Aykut %A Vrudhula, Sarma B. K. %B DAC %D 2017 %I ACM %K dblp %P 67:1-67:6 %T A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits. %U http://dblp.uni-trier.de/db/conf/dac/dac2017.html#KulkarniDV17 %@ 978-1-4503-4927-7

@inproceedings{conf/dac/KulkarniDV17, added-at = {2018-11-06T00:00:00.000+0100}, author = {Kulkarni, Niranjan and Dengi, Aykut and Vrudhula, Sarma B. K.}, biburl = {https://www.bibsonomy.org/bibtex/2545c0913ac6816ab19688d627fc80c2c/dblp}, booktitle = {DAC}, crossref = {conf/dac/2017}, ee = {https://doi.org/10.1145/3061639.3062183}, interhash = {d976a34765861527b321616a655d57b7}, intrahash = {545c0913ac6816ab19688d627fc80c2c}, isbn = {978-1-4503-4927-7}, keywords = {dblp}, pages = {67:1-67:6}, publisher = {ACM}, timestamp = {2018-11-07T13:09:51.000+0100}, title = {A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2017.html#KulkarniDV17}, year = 2017 }