%0 Conference Paper %1 conf/asicon/WangCLCMH11 %A Wang, Jinn-Shyan %A Chien, Yung-Chen %A Lin, Jia-Hong %A Cheng, Chun-Yuan %A Ma, Ying-Ting %A Huang, Chung-Hsun %B ASICON %D 2011 %I IEEE %K dblp %P 47-50 %T ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. %U http://dblp.uni-trier.de/db/conf/asicon/asicon2011.html#WangCLCMH11 %@ 978-1-61284-192-2

@inproceedings{conf/asicon/WangCLCMH11, added-at = {2016-06-22T00:00:00.000+0200}, author = {Wang, Jinn-Shyan and Chien, Yung-Chen and Lin, Jia-Hong and Cheng, Chun-Yuan and Ma, Ying-Ting and Huang, Chung-Hsun}, biburl = {https://www.bibsonomy.org/bibtex/2f3f6c995c1f98b39e1a8189488abc774/dblp}, booktitle = {ASICON}, crossref = {conf/asicon/2011}, ee = {http://dx.doi.org/10.1109/ASICON.2011.6157119}, interhash = {e1d549a07f269ac7d0f4f0b2ca27289d}, intrahash = {f3f6c995c1f98b39e1a8189488abc774}, isbn = {978-1-61284-192-2}, keywords = {dblp}, pages = {47-50}, publisher = {IEEE}, timestamp = {2016-06-23T11:39:00.000+0200}, title = {ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs.}, url = {http://dblp.uni-trier.de/db/conf/asicon/asicon2011.html#WangCLCMH11}, year = 2011 }