%0 Conference Paper %1 conf/cdes/EratneRJ10 %A Eratne, Savithra %A Romo, Claudia %A John, Eugene %B CDES %D 2010 %E Arabnia, Hamid R. %E Solo, Ashu M. G. %I CSREA Press %K dblp %P 61-66 %T Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase. %U http://dblp.uni-trier.de/db/conf/cdes/cdes2010.html#EratneRJ10 %@ 1-60132-135-X

@inproceedings{conf/cdes/EratneRJ10, added-at = {2010-12-06T00:00:00.000+0100}, author = {Eratne, Savithra and Romo, Claudia and John, Eugene}, biburl = {https://www.bibsonomy.org/bibtex/231a247bea18de10914c1bfddb33fce28/dblp}, booktitle = {CDES}, crossref = {conf/cdes/2010}, editor = {Arabnia, Hamid R. and Solo, Ashu M. G.}, interhash = {e25442401586504eec59bf2f569aaf8f}, intrahash = {31a247bea18de10914c1bfddb33fce28}, isbn = {1-60132-135-X}, keywords = {dblp}, pages = {61-66}, publisher = {CSREA Press}, timestamp = {2010-12-07T11:34:08.000+0100}, title = {Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase.}, url = {http://dblp.uni-trier.de/db/conf/cdes/cdes2010.html#EratneRJ10}, year = 2010 }