%0 Conference Paper %1 conf/aspdac/SogoTK13 %A Sogo, Kenta %A Toya, Akihiro %A Kikkawa, Takamaro %B ASP-DAC %D 2013 %I IEEE %K dblp %P 101-102 %T A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#SogoTK13 %@ 978-1-4673-3029-9

@inproceedings{conf/aspdac/SogoTK13, added-at = {2017-05-26T00:00:00.000+0200}, author = {Sogo, Kenta and Toya, Akihiro and Kikkawa, Takamaro}, biburl = {https://www.bibsonomy.org/bibtex/200d7914bcd016505703701a83ff39719/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2013}, ee = {https://doi.org/10.1109/ASPDAC.2013.6509576}, interhash = {e91e2483b38c414b603cc7afe358b9ee}, intrahash = {00d7914bcd016505703701a83ff39719}, isbn = {978-1-4673-3029-9}, keywords = {dblp}, pages = {101-102}, publisher = {IEEE}, timestamp = {2019-10-17T16:44:50.000+0200}, title = {A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#SogoTK13}, year = 2013 }