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A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption.

K. Sogo, A. Toya, and T. Kikkawa. ASP-DAC, page 101-102. IEEE, (2013)

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Design technology co-optimization for 10 nm and beyond.T. Kikkawa, and R. Joshi. CICC, page 1. IEEE, (2014)Tumor response extraction based on ensemble empirical mode decomposition for early breast cancer detection by UWB.Q. Li, X. Xiao, H. Song, L. Wang, and T. Kikkawa. BioCAS, page 97-100. IEEE, (2014)An adaptive window-based hybrid artifact removal method for Ultra-Wide Band imaging enhancement of early breast cancer detection.G. Liu, X. Xiao, H. Song, M. Lu, and T. Kikkawa. Biomed. Signal Process. Control., (2021)Accurate construction of 3-D numerical breast models with anatomical information through MRI scans.M. Lu, X. Xiao, H. Song, G. Liu, H. Lu, and T. Kikkawa. Comput. Biol. Medicine, (2021)Cross-Correlation of Confocal Images for Excised Breast Tissues of Total Mastectomy.H. Song, S. Sasada, T. Kadoya, K. Arihiro, M. Okada, X. Xiao, T. Ishikawa, D. O'Loughlin, J. ichi Takada, and T. Kikkawa. IEEE Trans. Biomed. Eng., 71 (5): 1705-1716 (May 2024)A 2- to 12-GHz 65-nm transmit/receive CMOS DP8T switching matrix for ultra-wideband antenna arrays.A. Azhari, and T. Kikkawa. I. J. Circuit Theory and Applications, 47 (8): 1293-1301 (2019)A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter.K. Sogo, A. Toya, and T. Kikkawa. ESSCIRC, page 253-256. IEEE, (2012)A 500 Mb/s Differential Input Non-coherent BPSK Receiver for UWB-IR Communication.M. Hafiz, N. Sasaki, and T. Kikkawa. IEICE Trans. Electron., 94-C (4): 567-574 (2011)Combined Approach to Estimate Blood Glucose Level in Noninvasive Monitoring: Ultra-Wide Band Microwave and Cascaded General Regression Neural Network.Z. Wang, X. Xiao, C. Yang, and T. Kikkawa. IEEE Trans. Ind. Informatics, 18 (8): 5105-5114 (2022)Comparative study on dielectric constants and conductivities of invasive ductal carcinoma tissues.T. Sugitani, K. Arihiro, and T. Kikkawa. EMBC, page 4387-4390. IEEE, (2015)

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A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption.

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A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption.