%0 Conference Paper %1 conf/vlsic/LiTYLCHLLKHCXS16 %A Li, Chao-Chieh %A Tsai, Tsung-Hsien %A Yuan, Min-Shueh %A Liao, Chia-Chun %A Chang, Chih-Hsien %A Huang, Tien-Chien %A Liao, Hsien-Yuan %A Lu, Chung-Ting %A Kuo, Hung-Yi %A Hsieh, Kenny %A Chen, Mark %A Ximenes, Augusto Ronchini %A Staszewski, Robert Bogdan %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#LiTYLCHLLKHCXS16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/LiTYLCHLLKHCXS16, added-at = {2021-03-10T00:00:00.000+0100}, author = {Li, Chao-Chieh and Tsai, Tsung-Hsien and Yuan, Min-Shueh and Liao, Chia-Chun and Chang, Chih-Hsien and Huang, Tien-Chien and Liao, Hsien-Yuan and Lu, Chung-Ting and Kuo, Hung-Yi and Hsieh, Kenny and Chen, Mark and Ximenes, Augusto Ronchini and Staszewski, Robert Bogdan}, biburl = {https://www.bibsonomy.org/bibtex/28077706424b0c36d57e3c30c2714f405/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {https://www.wikidata.org/entity/Q58929471}, interhash = {edb920df1257eeb17ded3ea9d7412194}, intrahash = {8077706424b0c36d57e3c30c2714f405}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-10T15:34:06.000+0200}, title = {A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#LiTYLCHLLKHCXS16}, year = 2016 }