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A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.

C. Li, T. Tsai, M. Yuan, C. Liao, C. Chang, T. Huang, H. Liao, C. Lu, H. Kuo, K. Hsieh, M. Chen, A. Ximenes, and R. Staszewski. VLSI Circuits, page 1-2. IEEE, (2016)

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Tsing-Tshih Tsung

Jieh-Wen Tsung

Linda Hsien

Wei-Ding Tsai

Other publications of authors with the same name

Sky recognitions for driving-view images.Y. Chen, and T. Tsai. ICVES, page 119-124. IEEE, (2013)Comparison of Several Confidence Intervals for Median Residual Lifetime with Left-truncated and Right-censored Data.Y. Chi, T. Tsai, Y. Tu, and W. Tsai. Communications in Statistics - Simulation and Computation, 45 (2): 701-716 (2016)A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS.C. Li, M. Yuan, C. Liao, C. Chang, Y. Lin, T. Tsai, T. Huang, H. Liao, C. Lu, H. Kuo and 2 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 68 (5): 1881-1891 (2021)Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight.N. Chang, T. Tsai, P. Hsu, Y. Chen, and T. Chang. IEEE Trans. Circuits Syst. Video Techn., 20 (6): 792-805 (2010)A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS.W. Chen, C. Wen, C. Fu, T. Tsai, Y. Chen, W. Huang, C. Tsai, A. Loke, and C. Kenny. VLSI Circuits, page 1-2. IEEE, (2020)Data reuse analysis of local stereo matching.T. Tsai, N. Chang, and T. Chang. ISCAS, page 812-815. IEEE, (2008)14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S.T. Tsai, M. Yuan, C. Chang, C. Liao, C. Li, and R. Staszewski. ISSCC, page 1-3. IEEE, (2015)A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector.Y. Liu, W. Chen, M. Chou, T. Tsai, Y. Lee, and M. Yuan. CICC, page 1-4. IEEE, (2013)A temporal case retrieval model to predict railway passenger arrivals.T. Tsai. Expert Syst. Appl., 36 (5): 8876-8882 (2009)Real-Time DSP Implementation on Local Stereo Matching.N. Chang, T. Lin, T. Tsai, Y. Tseng, and T. Chang. ICME, page 2090-2093. IEEE Computer Society, (2007)

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Disambiguation of "Tsai, Tsung-Hsien"

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A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.

Please choose a person to relate this publication to

Tsing-Tshih Tsung

Jieh-Wen Tsung

Linda Hsien

Wei-Ding Tsai

Wei-Ding Tsai

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tsai, Tsung-Hsien"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.

Please choose a person to relate this publication to

Tsing-Tshih Tsung

Jieh-Wen Tsung

Linda Hsien

Wei-Ding Tsai

Wei-Ding Tsai

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.