%0 Conference Paper %1 conf/vlsid/KumarVV08 %A Kumar, Nidhir %A Velu, Senthil N. %A Verma, Rajan %B VLSI Design %D 2008 %I IEEE Computer Society %K dblp %P 3-4 %T Gateway to Chips: High Speed I/O Signalling and Interface. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2008.html#KumarVV08 %@ 0-7695-3083-4

@inproceedings{conf/vlsid/KumarVV08, added-at = {2023-03-24T00:00:00.000+0100}, author = {Kumar, Nidhir and Velu, Senthil N. and Verma, Rajan}, biburl = {https://www.bibsonomy.org/bibtex/22cec397c18d52babc4b32423fd718d6b/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2008}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSI.2008.121}, interhash = {fb620bae75507a74306887f73d352be3}, intrahash = {2cec397c18d52babc4b32423fd718d6b}, isbn = {0-7695-3083-4}, keywords = {dblp}, pages = {3-4}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:19:22.000+0200}, title = {Gateway to Chips: High Speed I/O Signalling and Interface.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2008.html#KumarVV08}, year = 2008 }