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Disambiguation of "Amano, Hideharu"

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The Design of Scalable Stochastic Biochemical Simulator on FPGA.

, , , , , , , , and . FPT, page 339-340. IEEE, (2005)

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Hideharu Umehara

Kyoko Amano

Yu Amano

Shun'ichi Amano

 

Other publications of authors with the same name

Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device., , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 171-180. Springer, (2003)A prototype chip of multicontext FPGA with DRAM for virtual hardware., , and . ASP-DAC, page 17-18. ACM, (2001)An LSI implementation of the simple serial synchronized multistage interconnection network., , and . ASP-DAC, page 673-674. IEEE, (1997)Power reduction techniques for Dynamically Reconfigurable Processor Arrays., , , , , , , and . FPL, page 305-310. IEEE, (2008)A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration., , and . MCSoC, page 32-37. IEEE, (2019)A speculative gather system for Cool Mega-Array., , , , , and . FPT, page 346-349. IEEE, (2013)Variable pipeline structure for Coarse Grained Reconfigurable Array CMA., , , and . FPT, page 217-220. IEEE, (2016)Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel., and . CANDAR Workshops, page 280-284. IEEE, (2019)Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays., , , , , , and . FPT, page 273-276. IEEE, (2007)The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator., , and . FPT, page 1-4. IEEE, (2011)