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Disambiguation of "Ooi, Chia Yee"

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Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique.

, , and . Int. J. Reconfigurable Comput., (2015)

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Chia Ching Ooi

Charles Woei-Jye Yee

Hernani Tiago Yee Madeira

Sun Yee

Yeong Hui Yee

 

Other publications of authors with the same name

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation., , and . IEICE Trans. Inf. Syst., 90-D (8): 1202-1212 (2007)A New Design-for-Testability Method Based on Thru-Testability., and . J. Electron. Test., 27 (5): 583-598 (2011)Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique., , and . Int. J. Reconfigurable Comput., (2015)Built-in Self Test Power and Test Time Analysis in On-chip Networks., , , and . Circuits Syst. Signal Process., 34 (4): 1057-1075 (2015)A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (9): 1535-1544 (2008)Register-Transfer-Level Features for Machine-Learning-Based Hardware Trojan Detection., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (2): 502-509 (2020)Thermal Model with Metal Consideration for System-on-Chip Testing., and . J. Low Power Electron., 10 (3): 325-333 (2014)Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level., , , , , , , and . ATS, page 98. IEEE, (2019)Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms., , , , and . FCCM, page 102. IEEE Computer Society, (2015)Virtual Channel and Switch Allocation for Low Latency Network-on-Chip Routers., , and . FCCM, page 234. IEEE Computer Society, (2015)