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Disambiguation of "Makris, Yiorgos"

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On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD.

, , , and . IOLTS, page 123-128. IEEE Computer Society, (2008)

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Phokion Makris

Georgios Makris

Jannis Makris

Makris Wassilios

Panagiotis Makris

 

Other publications of authors with the same name

Hardware-Based Real-Time Workload Forensics., , and . IEEE Des. Test, 37 (4): 52-58 (2020)On the identification of modular test requirements for low cost hierarchical test path construction., and . Integr., 40 (3): 315-325 (2007)Guest Editors' Introduction: Special Section on Chips and Architectures for Emerging Technologies and Applications., , and . IEEE Trans. Computers, 60 (4): 450-451 (2011)Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (12): 2120-2133 (2017)On Improving Hotspot Detection Through Synthetic Pattern-Based Database Enhancement., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (12): 2522-2527 (2021)Nonlinear decision boundaries for testing analog circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1760-1773 (2005)Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (11): 2447-2460 (2015)VeriCoq: A Verilog-to-Coq converter for proof-carrying hardware automation., and . ISCAS, page 29-32. IEEE, (2015)SPIN-TEST: automatic test pattern generation for speed-independent circuits., and . ICCAD, page 903-908. IEEE Computer Society / ACM, (2004)Analog Performance Locking through Neural Network-Based Biasing., , , , , and . VTS, page 1-6. IEEE, (2019)