From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (12): 1914-1927 (2014)Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (12): 1857-1866 (2012)ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (9): 1315-1327 (2010)Simultaneous Layout Migration and Decomposition for Double Patterning Technology., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (2): 284-294 (2011)Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (6): 817-828 (2011)Voltage-Island Partitioning and Floorplanning Under Timing Constraints., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (5): 690-702 (2009)Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (5): 711-721 (2010)Generic ILP-based approaches for time-multiplexed FPGA partitioning., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (10): 1266-1274 (2001)Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (12): 2066-2079 (2017)A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (2): 193-206 (2009)