( en | de | ru )

 

Disambiguation of "Jutman, Artur"

Author of the publication

copydeleteadd this publication to your clipboard
Practical works for on-line teaching design and test of digital circuits.

, , , and . ICECS, page 1223-1226. IEEE, (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Artur Teuscher

Artur Budnowski

Artur Wiesmeier

Artur Spering

Artur Meyer

 

Other publications of authors with the same name

Structural fault collapsing by superposition of BDDs for test generation in digital circuits., , , and . ISQED, page 250-257. IEEE, (2010)Effective Scalable IEEE 1687 Instrumentation Network for Fault Management., , and . IEEE Des. Test, 30 (5): 26-35 (2013)HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study., , , and . CoRR, (2022)Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits., , , , and . DSD, page 658-663. IEEE Computer Society, (2010)At-speed on-chip diagnosis of board-level interconnect faults.. ETS, page 2-7. IEEE Computer Society, (2004)Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs., , , and . LATW, page 97-102. IEEE, (2006)Calculation of LFSR Seed and Polynomial Pair for BIST Applications., , and . DDECS, page 275-278. IEEE Computer Society, (2008)Timing simulation of digital circuits with binary decision diagrams., , and . DATE, page 460-466. IEEE Computer Society, (2001)On in-system programming of non-volatile memories., , , and . MIXDES, page 408-413. IEEE, (2013)DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits., , , , and . IEEE Trans. Ind. Electron., 55 (6): 2405-2415 (2008)