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Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-Efficiency., , and . FPL, page 371. IEEE, (2020)MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1663-1673 (2022)CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost., , , , , , , and . HPCA, page 593-612. IEEE, (2024)Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis., , , , , , , , , and . HPCA, page 280-296. IEEE, (2024)An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration., , , , , , , , and . DSN, page 138-149. IEEE, (2020)Leveraging Adversarial Detection to Enable Scalable and Low Overhead RowHammer Mitigations., , , , , , , and . CoRR, (2024)ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation., , , , , , , , and . CoRR, (2023)PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips., , , , , , , , , and 1 other author(s). CoRR, (2023)Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions., , , , , , and . HPCA, page 560-577. IEEE, (2024)Amplifying Main Memory-Based Timing Covert and Side Channels using Processing-in-Memory Operations., , , , , , , , and . CoRR, (2024)