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Disambiguation of "Hariyama, Masanori"

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An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture.

, , , and . ASP-DAC, page 89-90. IEEE, (2011)

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Other publications of authors with the same name

Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , and . MWSCAS, page 1-4. IEEE, (2022)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , , and . ERSA, page 309-310. CSREA Press, (2008)Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits., , and . ISVLSI, page 243-248. IEEE Computer Society, (2004)Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , and . ISMVL, page 17. IEEE Computer Society, (2006)A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment., and . APCCAS, page 1803-1806. IEEE, (2006)An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture., , , and . ASP-DAC, page 89-90. IEEE, (2011)Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems., , , and . SCFA, volume 10776 of Lecture Notes in Computer Science, page 146-155. Springer, (2018)A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA., , , , , , and . CANDAR Workshops, page 103-108. IEEE, (2019)