Author of the publication

Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks.

, , , and . VLSI Design, page 248-253. IEEE Computer Society, (2001)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Power-Area Trade-Offs in Divided Word Line Memory Arrays., , and . Journal of Circuits, Systems, and Computers, 7 (1): 49-68 (1997)Using Memory Compression for Energy Reduction in an Embedded Java System., , , , and . Journal of Circuits, Systems, and Computers, 11 (5): 537-556 (2002)Accurate Estimation of Combinational Circuit Activity., , , and . DAC, page 618-622. ACM Press, (1995)Validation of an Architectural Level Power Analysis Technique., , , and . DAC, page 242-245. ACM Press, (1998)Reduction of broadband noise in speech by spectral weighting.. ICASSP, page 1045-1051. IEEE, (1980)Efficiently computing communication complexity for multilevel logic synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (5): 545-554 (1992)Exploiting communication complexity for multilevel logic synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (10): 1017-1027 (1990)A hybrid NoC design for cache coherence optimization for chip multiprocessors., , , , , and . DAC, page 834-842. ACM, (2012)Secretary/Treasurer's Report.. SIGARCH Comput. Archit. News, 14 (4): 28 (1986)Exploring performance-power tradeoffs in providing reliability for NoC-based MPSoCs., , and . ISQED, page 495-501. IEEE, (2011)