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High throughput 2D DCT/IDCT processor for video coding., , и . ICIP (3), стр. 1036-1039. IEEE, (2005)Parallel-pipelined architecture for 2-D ICT VLSI implementation., , и . ICIP (3), стр. 89-92. IEEE, (2003)An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC., и . Signal Process. Image Commun., 26 (6): 289-303 (2011)An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV., и . J. Signal Process. Syst., 62 (3): 443-457 (2011)A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC., , и . J. Signal Process. Syst., 70 (1): 59-73 (2013)An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit., и . Microelectron. J., 35 (12): 939-944 (2004)High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip., , и . VLSI Signal Processing, 45 (3): 161-175 (2006)Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits".. IEEE J. Solid State Circuits, 35 (10): 1517 (2000)Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits.. IEEE J. Solid State Circuits, 33 (4): 604-613 (1998)Parallel-pipeline 8×8 forward 2-D ICT processor chip for image coding., , и . IEEE Trans. Signal Process., 53 (2-1): 714-723 (2005)