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Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs.

F. Ren, H. Park, C. Yang, and D. Markovic. IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (11): 2932-2939 (2013)

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Michaela Karin Ingrid Henry

Madeleine Mary Henry

James Henry

David P Henry

Marie-Louise Henry

Other publications of authors with the same name

Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter.H. Park, and C. Yang. IEEE Trans. Circuits Syst. II Express Briefs, 59-II (9): 563-567 (2012)Male Adolescents' and Young Adults' Evaluations of Interracial Exclusion in Offline and Online Settings.H. Park, S. Gönültas, K. Mulvey, M. Killen, and M. Ruck. Cyberpsychology Behav. Soc. Netw., 22 (10): 641-647 (2019)A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology.T. Ali, R. Yousry, H. Park, E. Chen, P. Weng, Y. Huang, C. Liu, C. Wu, S. Huang, C. Lin and 9 other author(s). ISSCC, page 118-120. IEEE, (2019)A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS.R. Yousry, H. Park, E. Chen, and C. Yang. ISCAS, page 2443-2447. IEEE, (2013)Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression.H. Park, and C. Yang. IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 27-38 (2014)A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET.H. Park, M. Abdullatif, E. Chen, A. Elmallah, Q. Nehal, M. Gandara, T. Liu, A. Khashaba, J. Lee, C. Kuan and 11 other author(s). ISSCC, page 110-111. IEEE, (2023)A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS.T. Ali, L. Rao, U. Singh, M. Abdul-Latif, Y. Liu, A. Hafez, H. Park, A. Vasani, Z. Huang, A. Iyer and 3 other author(s). VLSIC, page 348-. IEEE, (2015)Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs.F. Ren, H. Park, C. Yang, and D. Markovic. IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (11): 2932-2939 (2013)An INL Yield Model of the Digital-to-Analog Converter.H. Park, and C. Yang. IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (3): 582-592 (2013)A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.N. Kocaman, T. Ali, L. Rao, U. Singh, M. Abdul-Latif, Y. Liu, A. Hafez, H. Park, A. Vasani, Z. Huang and 3 other author(s). IEEE J. Solid State Circuits, 51 (4): 881-892 (2016)

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Disambiguation of "Park, Henry"

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Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs.

Please choose a person to relate this publication to

Michaela Karin Ingrid Henry

Madeleine Mary Henry

James Henry

David P Henry

Marie-Louise Henry

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Park, Henry"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs.

Please choose a person to relate this publication to

Michaela Karin Ingrid Henry

Madeleine Mary Henry

James Henry

David P Henry

Marie-Louise Henry

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs.