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Disambiguation of "Inoue, Yasuaki"

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A GIDL-Current Model for Advanced MOSFET Technologies without Binning.

, , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)

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Yasuaki Saigusa

Heide Inoue

Tomoyuki Inoue

Hiroko Inoue

Norman Inoue

 

Other publications of authors with the same name

A low voltage CMOS rectifier for wirelessly powered devices., , , and . ISCAS, page 873-876. IEEE, (2010)A CMOS Sub-l-V nanopower current and voltage reference with leakage compensation., , and . ISCAS, page 4069-4072. IEEE, (2010)A high efficiency CMOS rectifier with ON-OFF response compensation for wireless power transfer in biomedical applications., , and . ISIC, page 91-94. IEEE, (2014)An interval algorithm for finding all solutions of nonlinear resistive circuits., , and . ISCAS (3), page 192-195. IEEE, (2003)A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback., , and . IEICE Trans. Electron., 92-C (6): 806-814 (2009)A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (4): 748-755 (2007)Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3412-3420 (2005)Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3367-3374 (2005)Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (10): 2531-2539 (2009)A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (10): 2562-2569 (2005)