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Estimating the locking range of analog dividers through a phase-domain macromodel., , , and . ISCAS, page 1535-1538. IEEE, (2010)Digital signal Processor-based Investigation of Chua's Circuit family., , , and . Chua's Circuit, volume 1 of World Scientific Series on Nonlinear Science Series B, World Scientific, (1993)Spurious tones in digital delta-sigma modulators resulting from pseudorandom dither., , and . J. Frankl. Inst., 352 (8): 3325-3344 (2015)0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital Δ-Σ Modulator-Based Divider Controller., , , , , and . IEEE J. Solid State Circuits, 49 (7): 1595-1605 (2014)Wandering Spurs in MASH 1-1 Delta-Sigma Modulators., and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (7): 2426-2439 (2019)Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking - Part II: Non-Constant Input., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 1980-1991 (2012)Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part I: Qualitative Analysis., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (1): 179-188 (2010)Modelling and Verification of Nonlinear Electromechanical Coupling in Micro-Scale Kinetic Electromagnetic Energy Harvesters., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (2): 565-577 (2020)Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM., and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (4): 714-726 (2009)Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking - Part I: Constant Input., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (9): 2137-2148 (2011)