( en | de | ru )

 

Disambiguation of "Patkar, Sachin B."

Author of the publication

copydeleteadd this publication to your clipboard
Parallel two step random walk algorithm to analyze VLSI power grid networks.

, , , , and . VDAT, page 1-2. IEEE Computer Society, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sachin Arora

Sachin Deshmukh

Sachin Kinge

Sachin Chhatwani

Sachin Kumar

 

Other publications of authors with the same name

FPGA Implementation of Particle Filter Based Object Tracking in Video., , , and . ISED, page 82-86. IEEE, (2012)Solution of PDEs-electrically coupled systems with electrical analogy., , and . Integr., 46 (4): 427-440 (2013)Algorithms For Scheduling Of Data Transfer Across FPGAs In A Grid., and . ERSA, page 255-260. CSREA Press, (2005)Scalable implementation of particle filter-based visual object tracking on network-on-chip (NoC)., , and . J. Real Time Image Process., 17 (5): 1117-1134 (2020)Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style., , , , , , , and . CoRR, (2023)MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory., , , , , , and . CoRR, (2023)Real time System Implementation for Stereo 3D Mapping and Visual Odometry., , , , and . IPAS, page 7-13. IEEE, (2020)Approximation Algorithms for Min-k-Overlap Problems Using the Principal Lattice of Partitions Approach., , and . J. Algorithms, 21 (2): 306-330 (1996)CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism., , , , , , and . J. Syst. Archit., (February 2023)Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar., , , , , , and . NEWCAS, page 1-5. IEEE, (2023)