( en | de | ru )

 

Disambiguation of "Yúfera, Víctor Viñals"

Author of the publication

copydeleteadd this publication to your clipboard
A fault-tolerant last level cache for CMPs operating at ultra-low voltage.

, , , , , and . J. Parallel Distributed Comput., (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Víctor Farías

Víctor Castaño

Víctor Jiménez

Víctor Uc-Cetina

Reinforcement learning in continuous state and action spaces. HU Berlin, (2009)

Víctor Olmos León

 

Other publications of authors with the same name

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches., , , and . IEEE Access, (2020)BALANCER: bandwidth allocation and cache partitioning for multicore processors., , , and . J. Supercomput., 79 (9): 10252-10276 (June 2023)A proposal to introduce power and energy notions in computer architecture laboratories., , and . WCAE, page 52-57. ACM, (2007)Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (7): 2081-2094 (2017)Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor., , , , , and . IEEE ACM Trans. Comput. Biol. Bioinform., 17 (4): 1093-1104 (2020)Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping., , , , and . ACM Trans. Archit. Code Optim., 11 (2): 19:1-19:26 (2014)LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (8): 1510-1523 (2012)Store Buffer Design for Multibanked Data Caches., , , and . IEEE Trans. Computers, 58 (10): 1307-1320 (2009)A fault-tolerant last level cache for CMPs operating at ultra-low voltage., , , , , and . J. Parallel Distributed Comput., (2019)Analysis of network-on-chip topologies for cost-efficient chip multiprocessors., , , , and . Microprocess. Microsystems, (2016)