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Disambiguation of "Chen, Tung-Chieh"

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MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (9): 1621-1634 (2008)

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Nan-chieh Chen

Tsung-Chieh Chen

Mou-Chieh Chen

Pan-Chieh Chen

Liang-Chieh Chen

 

Other publications of authors with the same name

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (12): 1914-1927 (2014)Effective Wire Models for X-Architecture Placement., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (4): 654-658 (2008)An integrated nonlinear placement framework with congestion and porosity aware buffer planning., , and . DAC, page 702-707. ACM, (2008)X-architecture placement based on effective wire models., , and . ISPD, page 87-94. ACM, (2007)MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs., , , and . ASP-DAC, page 557-562. ACM, (2019)SoC test scheduling using the B-tree based floorplanning technique., , and . ASP-DAC, page 1188-1191. ACM Press, (2005)A novel damped-wave framework for macro placement., , and . ICCAD, page 504-511. IEEE, (2017)MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (9): 1621-1634 (2008)Essential Issues in Analytical Placement Algorithms., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Double patterning lithography-aware analog placement., , , , and . DAC, page 4:1-4:6. ACM, (2013)