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Disambiguation of "Park, Hong-June"

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A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation.

, , , and . ISSCC, page 140-142. IEEE, (2012)

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June Park

Hong-June Kuo

Hong-Yang Park

Hong-Suck Park

Joo-Hong Park

 

Other publications of authors with the same name

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation., , , and . IEEE J. Solid State Circuits, 48 (9): 2118-2127 (2013)A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement., , , , , and . IEEE J. Solid State Circuits, 51 (8): 1902-1914 (2016)A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (5): 629-642 (1991)Analysis and prevention of DRAM latch-up during power-on., , , , , , , , and . IEEE J. Solid State Circuits, 32 (1): 79-85 (1997)A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines., , , , and . IEEE J. Solid State Circuits, 47 (9): 2068-2079 (2012)A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme., , , , , and . IEEE J. Solid State Circuits, 37 (2): 245-250 (2002)A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation., , and . IEEE J. Solid State Circuits, 41 (3): 633-641 (2006)A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration., , , , , and . ISSCC, page 112-113. IEEE, (2008)5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop., , , , and . ISSCC, page 94-95. IEEE, (2017)Deadzone-Minimized Systematic Offset-Free Phase Detectors., , , and . IEICE Trans. Electron., 91-C (9): 1525-1528 (2008)