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Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform.

, , , , , , , and . ASP-DAC, page 317-322. IEEE, (2009)

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Data Path Testability Analysis Based on BDDs., , and . ISCAS, page 2012-2014. IEEE, (1995)GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications., , and . ISCAS, page 912-915. IEEE, (1995)An Output/State Encoding for Self-Checking Finite State Machine., and . ISCAS, page 2136-2139. IEEE, (1995)Two-Dimensional Sequential Array Architectures: Design for Testability Approaches., , and . ISCAS, page 81-84. IEEE, (1994)Optimization techniques for multiple output function synthesis., , and . EURO-DAC, page 545-551. EEE Computer Society, (1991)ASSURE: RTL Locking Against an Untrusted Foundry., , , , and . CoRR, (2020)The Impact of Source Code Transformations on Software Power and Energy Consumption., , , and . Journal of Circuits, Systems, and Computers, 11 (5): 477-502 (2002)Coloring the cloud for predictable performance., , , , and . SoCC, page 47:1-47:2. ACM, (2013)An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures., , , , and . VLSI-SoC, page 146-151. IEEE, (2006)Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems., , , , and . ICSAMOS, page 142-149. IEEE, (2008)