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Disambiguation of "López-Paradís, Guillem"

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Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi.

, , , , , and . DATE, page 1-6. IEEE, (2023)

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Margarita López López

Claudia Carolina López Yomayuza

Charakterisierung der Tollwutvakzinen Rabipur und Rabivac und der enthaltenen Virusstämme FluryLEP und PM 1503. Uni Gießen, (2009)

Fátima López López Pielow

Metamorfosis y metáfora: mito y discurso en Pedro Calderón de la Barca y Ovidio. Uni Wuppertal, (2008)

José Braulio López Padilla

Caroline López

 

Other publications of authors with the same name

Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi., , , , , and . DATE, page 1-6. IEEE, (2023)Characterization of a Coherent Hardware Accelerator Framework for SoCs., , , and . SAMOS, volume 14385 of Lecture Notes in Computer Science, page 91-106. Springer, (2023)OpenPiton Optimizations Towards High Performance Manycores., , , , , , , , and . NoCArc@MICRO, page 27-33. ACM, (2023)Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology., , , , , , , , , and 38 other author(s). DCIS, page 1-6. IEEE, (2023)Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors., , , , , , , , , and 5 other author(s). DATE, page 136-141. IEEE, (2021)gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator., , and . ICPP, page 29:1-29:11. ACM, (2021)DVINO: A RISC-V Vector Processor Implemented in 65nm Technology., , , , , , , , , and 33 other author(s). DCIS, page 1-6. IEEE, (2022)An Academic RISC-V Silicon Implementation Based on Open-Source Components., , , , , , , , , and 24 other author(s). DCIS, page 1-6. IEEE, (2020)GenArchBench: A genomics benchmark suite for arm HPC processors., , , , , , , , , and 5 other author(s). Future Gener. Comput. Syst., (2024)Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI., , , , , , , , , and . DSD, page 254-261. IEEE, (2022)