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High-performance hardware accelerators for sorting and managing priorities.

, , , and . DDECS, page 313-318. IEEE Computer Society, (2011)

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Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs., , and . FPL, volume 1673 of Lecture Notes in Computer Science, page 313-322. Springer, (1999)Application-specific hardware accelerator for implementing recursive sorting algorithms., , , and . FPT, page 269-272. IEEE, (2010)Design space exploration in multi-level computing systems., , , and . CompSysTech, page 40-47. ACM, (2014)Recursive and Iterative Algorithms for N-ary Search Problems., and . IFIP PPAI, volume 4170 of Lecture Notes in Computer Science, page 81-90. Springer, (2006)Dynamically Reconfigurable Implementation of Control Circuits., and . VLSI, volume 162 of IFIP Conference Proceedings, page 137-148. Kluwer, (1999)Reuse Technique in Hardware Design., and . IRI, page 36-41. IEEE Systems, Man, and Cybernetics Society, (2007)Hardware/software modeling of FPGA-based systems.. Parallel Algorithms Appl., 17 (1): 19-39 (2002)Data processing in the firmware systems for logic control based on search networks., and . Autom. Remote. Control., 78 (1): 100-112 (2017)Synthesis Tools and Design Environment for Dynamically Reconfigurable FPGAs., , , , , , , and . SBCCI, page 46-50. IEEE Computer Society, (1998)A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors., , , and . DSD, page 222-229. IEEE Computer Society, (2003)