( en | de | ru )

 

Disambiguation of "Zhang, Chunyuan"

Author of the publication

copydeleteadd this publication to your clipboard
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs.

, , , , and . ISCAS, page 1-5. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chunyuan Chi

Zhang Zhang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)

Yan Zhang

Xianghong Zhang

 

Other publications of authors with the same name

Transform coding on programmable stream processors., , , and . J. Supercomput., 45 (1): 66-87 (2008)Deep Learning Research and Development Platform: Characterizing and Scheduling with QoS Guarantees on GPU Clusters., , , , , , and . IEEE Trans. Parallel Distributed Syst., 31 (1): 34-50 (2020)High efficient sedimentary basin simulations on hybrid CPU-GPU clusters., , , , , and . Clust. Comput., 17 (2): 359-369 (2014)A Computational Model of the Short-Cut Rule for 2D Shape Decomposition., , , and . IEEE Trans. Image Process., 24 (1): 273-283 (2015)MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA., , , , and . IEICE Electron. Express, 15 (10): 20180286 (2018)A fault detection mechanism in a Data-flow scheduled Multithreaded processor., , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Accelerated Motion Estimation of H.264 on Imagine Stream Processor., , , , , and . ICIAR, volume 3656 of Lecture Notes in Computer Science, page 367-374. Springer, (2005)Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System., , , , and . FPGA, page 117. ACM, (2019)Extending BORPH for shared memory reconfigurable computers., , , , and . FPL, page 563-566. IEEE, (2012)Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA., , , , and . INFOCOM Workshops, page 1057-1058. IEEE, (2019)