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Automatic bus macro placement for partially reconfigurable FPGA designs., , and . FPGA, page 269-272. ACM, (2009)Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point., , , , , , , , , and 14 other author(s). NeurIPS, (2020)Architectural Support for Multilanguage Parallel Programming on Heterogeneous Systems., and . ASPLOS, page 21-30. ACM Press, (1987)SIGARCH Computer Architecture News 15(5), SIGOPS Operating System Review 21(4), SIGPLAN Notices 22(10).An MS-DOS Filesystem for UNIX., and . USENIX Winter, page 337-354. USENIX Association, (1994)Minimizing the runtime partial reconfiguration overheads in reconfigurable systems., , , and . J. Supercomput., 61 (3): 894-911 (2012)Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only)., , and . FPGA, page 292. ACM, (2010)MMLite: a highly componentized system architecture., and . ACM SIGOPS European Workshop, page 96-103. ACM, (1998)An overview of the Rialto real-time architecture., , , , , and . ACM SIGOPS European Workshop, page 249-256. ACM, (1996)Image Segmentation Using Hardware Forest Classifiers., , , , and . FCCM, page 73-80. IEEE Computer Society, (2013)An Extensible I/O Subsystem., , and . FCCM, page 269-270. IEEE Computer Society, (2008)