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Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints.

, , and . NOCS, page 185-192. IEEE Computer Society, (2012)

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Efficient implementation of distributed routing algorithms for NoCs., , , , and . IET Comput. Digit. Tech., 3 (5): 460-475 (2009)Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip., , , and . IET Comput. Digit. Tech., (2013)Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip., , , and . ACM Great Lakes Symposium on VLSI, page 125-128. ACM, (2009)Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels., and . AISTECS@HiPEAC, page 12-17. ACM, (2017)Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis., , , and . DATE, page 1589-1594. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Power aware network interface management for streaming multimedia., , and . WCNC, page 926-930. IEEE, (2002)SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs., , , and . Embedded Systems Design and Verification, CRC Press, (2009)Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip., , , and . Embedded Systems Design and Verification, CRC Press, (2009)Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform., , and . VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 87-112. Springer, (2020)Energy-Reliability trade-Off for NoCs., , and . Networks on Chip, Kluwer / Springer, (2003)